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preliminary revision 1.0, november 2001 key features single power supply operation ? read, program and erase operations from 2.7 to 3.6 volts ? ideal for battery-powered applications high performance ? 70 and 90 ns access time versions for full voltage range operation ? 55 ns access time version for operation from 3.0 to 3.6 volts ultra-low power consumption (typical values) ? automatic sleep mode current: 0.2 a ? standby mode current: 0.2 a ? read current: 7 ma (at 5 mhz) ? program/erase current: 15 ma flexible sector architecture: ? one 16 kb, two 8 kb, one 32 kb and seven 64 kb sectors in byte mode ? one 8 kw, two 4 kw, one 16 kw and seven 32 kw sectors in word mode ? top or bottom boot block configurations available sector protection ? allows locking of a sector or sectors to prevent program or erase operations within that sector ? sectors lockable in-system or via programming equipment ? temporary sector unprotect allows changes in locked sectors (requires high voltage on reset# pin) fast program and erase times ? sector erase time: 0.5 sec typical for each sector ? chip erase time: 5 sec typical ? byte program time: 9 s typical ? word program time: 11 s typical unlock bypass program command ? reduces programming time when issuing multiple program command sequences automatic erase algorithm preprograms and erases any combination of sectors or the entire chip automatic program algorithm writes and verifies data at specified addresses a[17:0] 18 ce# oe# reset# byte# we# 8 7 dq[7:0] dq[14:8] dq[15]/a[-1] ry/by# logic diagram minimum 100,000 write cycles per sector compatible with jedec standards ? pinout and software compatible with single-power supply flash devices ? superior inadvertent write protection data# polling and toggle bits ? provide software confirmation of completion of program and erase operations ready/busy# pin ? provides hardware confirmation of completion of program and erase operations erase suspend/erase resume ? suspends an erase operation to allow reading data from, or programming data to, a sector that is not being erased ? erase resume can then be invoked to complete suspended erasure hardware reset pin (reset#) resets the device to reading array data space efficient packaging ? 48-pin tsop and 48-ball fbga packages HY29LV400 4 mbit (512k x 8/256k x 16) low voltage flash memory
2 rev. 1.0/nov. 01 HY29LV400 general description the HY29LV400 is a 4 mbit, 3 volt-only, cmos flash memory organized as 524,288 (512k) bytes or 262,144 (256k) words that is available in 48- pin tsop and 48-ball fbga packages. word- wide data (x16) appears on dq[15:0] and byte- wide (x8) data appears on dq[7:0]. the HY29LV400 can be programmed and erased in-system with a single 3 volt v cc supply. inter- nally generated and regulated voltages are pro- vided for program and erase operations, so that the device does not require a higher voltage v pp power supply to perform those functions. the de- vice can also be programmed in standard eprom programmers. access times as low as 70 ns over the full operating voltage range of 2.7 - 3.6 volts are offered for timing compatibility with the zero wait state requirements of high speed micropro- cessors. a 55 ns version operating from 3.0 to 3.6 volts is also available. to eliminate bus con- tention, the HY29LV400 has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is compatible with the jedec single- power-supply flash command set standard. com- mands are written to the command register using standard microprocessor write timings. they are then routed to an internal state-machine that con- trols the erase and programming circuits. device programming is performed a byte/word at a time by executing the four-cycle program command write sequence. this initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. faster program- ming times can be achieved by placing the HY29LV400 in the unlock bypass mode, which requires only two write cycles to program data in- stead of four. the HY29LV400 ? s sector erase architecture allows any number of array sectors to be erased and re- programmed without affecting the data contents of other sectors. device erasure is initiated by executing the erase command sequence. this initiates an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. as during programming cycles, the device auto- matically times the erase pulse widths and veri- fies proper cell margin. hardware sector protec- tion optionally disables both program and erase operations in any combination of the sectors of the memory array, while temporary sector unpro- tect allows in-system erasure and code changes in previously protected sectors. erase suspend enables the user to put erase on hold for any pe- riod of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the de- vice is fully erased when shipped from the factory. addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the ry/by# pin, or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. hardware data protection measures include a low v cc detector that automatically inhibits write op- erations during power transitions. after a program or erase cycle has been com- pleted, or after assertion of the reset# pin (which terminates any operation in progress), the device is ready to read data or to accept another com- mand. reading data out of the device is similar to reading from other flash or eprom devices. two power-saving features are embodied in the HY29LV400. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. the host can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes.
3 rev. 1.0/nov. 01 HY29LV400 block diagram state control we# ce# oe# byte# command register dq[15:0] a[17:0, 1] v cc detector timer erase voltage generator and sector switches program voltage generator address latch x-decoder y-decoder 4 mb flash memory array (11 sectors) y-gating data latch i/o buffers i/o control reset# dq[15:0] a[17:0, -1] ry/by# signal descriptions e m a n e p y t n o i t p i r c s e d ] 0 : 7 1 [ as t u p n i . h g i h e v i t c a , s s e r d d a n i t u p n i ] 1 - [ a / ] 5 1 [ q d e h t h t i w d e n i b m o c , s t u p n i 8 1 e s e h t . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w n o i t a c o l e n o t c e l e s , e d o m e t y b , ] 1 - [ a / ] 5 1 [ q d ] 0 : 4 1 [ q d s t u p t u o / s t u p n i e t a t s - i r t h g i h e v i t c a , s u b a t a d d a e r r o f h t a p a t a d t i b - 6 1 r o - 8 n a e d i v o r p s n i p e s e h t . t i b - 9 1 e h t f o b s l e h t s a d e s u s i ] 1 - [ a / ] 5 1 [ q d , e d o m e t y b n i . s n o i t a r e p o e t i r w d n a . e d o m e t y b n i d e t a t s - i r t n i a m e r d n a d e s u n u e r a ] 8 : 4 1 [ q d . t u p n i s s e r d d a e t y b # e t y bt u p n i . w o l e v i t c a , e d o m e t y b . e d o m d r o w s t c e l e s h g i h , e d o m e t y b s t c e l e s w o l # e ct u p n i . w o l e v i t c a , e l b a n e p i h c r o m o r f a t a d d a e r o t d e t r e s s a e b t s u m t u p n i s i h t e h t d n a d e t a t s - i r t s i s u b a t a d e h t , h g i h n e h w . 0 0 4 v l 9 2 y h e h t o t a t a d e t i r w . e d o m y b d n a t s e h t n i d e c a l p s i e c i v e d # e ot u p n i w o l e v i t c a , e l b a n e t u p t u o r o f d e t a g e n d n a s n o i t a r e p o d a e r r o f d e t r e s s a . e h t g n i r u d d a e r s i d r o w a r o e t y b a r e h t e h w s e n i m r e t e d # e t y b . s n o i t a r e p o e t i r w . n o i t a r e p o d a e r # e wt u p n i . w o l e v i t c a , e l b a n e e t i r w d n a m m o c r o s d n a m m o c f o g n i t i r w s l o r t n o c e t i r w a . y a r r a y r o m e m e h t f o s r o t c e s e s a r e r o a t a d m a r g o r p o t r e d r o n i s e c n e u q e s h g i h s i # e o d n a w o l s i # e c e l i h w d e t r e s s a s i # e w n e h w e c a l p s e k a t n o i t a r e p o . # t e s e rt u p n i . w o l e v i t c a , t e s e r e r a w d r a h e h t g n i t t e s e r f o d o h t e m e r a w d r a h a s e d i v o r p y l e t a i d e m m i t i , t e s e r s i e c i v e d e h t n e h w . e t a t s y a r r a d a e r e h t o t 0 0 4 v l 9 2 y h e c i v e d e h t , d e t r e s s a s i # t e s e r e l i h w . s s e r g o r p n i n o i t a r e p o y n a s e t a n i m r e t . e d o m y b d n a t s e h t n i e b l l i w # y b / y r t u p t u o n i a r d n e p o . s u t a t s y s u b / y d a e r n i s i d n a m m o c e s a r e r o e t i r w a r e h t e h w s e t a c i d n i y l e v i t c a s i e c i v e d e h t e l i h w w o l s n i a m e r . d e t e l p m o c n e e b s a h r o s s e r g o r p . a t a d y a r r a d a e r o t y d a e r s i t i n e h w h g i h s e o g d n a , g n i s a r e r o a t a d g n i m m a r g o r p v c c - - . y l p p u s r e w o p ) l a n i m o n ( t l o v - 3 v s s - - . d n u o r g l a n g i s d n a r e w o p
4 rev. 1.0/nov. 01 HY29LV400 pin configurations a6 b6 c6 d6 e6 f6 g6 h6 a5 b5 c5 d5 e5 f5 g5 h5 a4 b4 c4 d4 e4 f4 g4 h4 a3 b3 c3 d3 e3 f3 g3 h3 a2 b2 c2 d2 e2 f2 g2 h2 a1 b1 c1 d1 e1 f1 g1 h1 a[13] a[12] a[14] a[15] a[16] byte# dq[15]/a[-1] v ss a[9] a[8] a[10] a[11] dq[7] dq[14] dq[13] dq[6] we# reset# nc nc dq[5] dq[12] v cc dq[4] ry/by# nc nc nc dq[2] dq[10] dq[11] dq[3] a[7] a[17] a[6] a[5] dq[0] dq[8] dq[9] dq[1] a[3] a[4] a[2] a[1] a[0] ce# oe# v ss 48-ball fbga (6 x 8 mm, top view, balls facing down) tsop48 dq7 dq14 44 43 dq6 dq13 42 41 dq5 dq12 40 39 dq4 v cc 38 37 dq11 dq3 36 35 dq10 dq2 34 33 dq9 dq1 32 31 dq8 dq0 30 29 a16 byte# 48 47 v ss dq15/a-1 46 45 oe# v ss 28 27 ce# a0 26 25 a11 a10 5 6 a9 a8 7 8 nc nc 9 10 we# reset# 11 12 nc nc 13 14 ry/by# nc 15 16 a17 a7 17 18 a6 a5 19 20 a15 a14 1 2 a13 a12 3 4 a4 a3 21 22 a2 a1 23 24
5 rev. 1.0/nov. 01 HY29LV400 conventions unless otherwise noted, a positive logic (active high) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (v ih ) causes assertion of the signal. a ? # ? symbol following the signal name, e.g., reset#, indicates that the signal is asserted in the low state (v il ). see dc specifications for v ih and v il values. whenever a signal is separated into numbered bits, e.g., dq[7], dq[6], ..., dq[0], the family of bits may also be shown collectively, e.g., as dq[7:0]. the designation 0xnnnn (n = 0, 1, 2, . . . , 9, a, . . . , e, f) indicates a number expressed in hexadeci- mal notation. the designation 0bxxxx indicates a number expressed in binary notation (x = 0, 1). memory array organization the 4 mbit flash memory array is organized into eleven blocks called sectors (s0, s1, . . . , s10). a sector is the smallest unit that can be erased and that can be protected to prevent accidental or unauthorized erasure. see the ? bus operations ? and ? command definitions ? sections of this docu- ment for additional information on these functions. in the HY29LV400, four of the sectors, which com- prise the boot block , vary in size from 8 to 32 kbytes (4 to 16 kwords), while the remaining seven sectors are uniformly sized at 64 kbytes (32 kwords). the boot block can be located at the bottom of the address range (HY29LV400b) or at the top of the address range (HY29LV400t). tables 1 and 2 define the sector addresses and corresponding address ranges for the top and bot- tom boot block versions of the HY29LV400. bus operations device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. the command register itself does not occupy any addressable memory location. the contents of the command register serve as inputs to an internal state ma- chine whose outputs control the operation of the device. table 3 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. certain bus operations require a high voltage on one or more device pins. those are described in table 4. read operation data is read from the HY29LV400 by using stan- dard microprocessor read cycles while placing the byte or word address on the device ? s address in- puts. the host system must drive the ce# and oe# pins low and drive we# high for a valid read operation to take place. the byte# pin determines whether the device outputs array data in words (dq[15:0]) or in bytes (dq[7:0]). the HY29LV400 is automatically set for reading array data after device power-up and after a hard- ware reset to ensure that no spurious alteration of the memory content occurs during the power tran- sition. no command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register con- tents are altered. this device features an erase suspend mode. while in this mode, the host may read the array data from any sector of memory that is not marked for erasure. if the host reads from an address within an erase-suspended (or erasing) sector, or while the device is performing a byte or word pro- gram operation, the device outputs status data instead of array data. after completing an auto- matic program or automatic erase algorithm within a sector, that sector automatically returns to the read array data mode. after completing a program- ming operation in the erase suspend mode, the system may once again read array data with the same exception noted above. the host must issue a hardware reset or the soft- ware reset command to return a sector to the read array data mode if dq[5] goes high during a pro- gram or erase cycle, or to return the device to the read array data mode while it is in the electronic id mode.
6 rev. 1.0/nov. 01 HY29LV400 table 2. HY29LV400b (bottom boot block) memory array organization table 1. HY29LV400t (top boot block) memory array organization r o t c e s e z i s ) w k / b k ( s s e r d d a r o t c e s 1 e d o m e t y b e g n a r s s e r d d a 3 , 2 e d o m d r o w e g n a r s s e r d d a 3 , 2 ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s2 3 / 4 6 000xxx f f f f 0 x 0 - 0 0 0 0 0 x 0f f f 7 0 x 0 - 0 0 0 0 0 x 0 1 s2 3 / 4 6 0 0 1xxx f f f f 1 x 0 - 0 0 0 0 1 x 0f f f f 0 x 0 - 0 0 0 8 0 x 0 2 s2 3 / 4 6 0 10xxx f f f f 2 x 0 - 0 0 0 0 2 x 0f f f 7 1 x 0 - 0 0 0 0 1 x 0 3 s2 3 / 4 6 0 1 1xxx f f f f 3 x 0 - 0 0 0 0 3 x 0f f f f 1 x 0 - 0 0 0 8 1 x 0 4 s2 3 / 4 6 10 0xxx f f f f 4 x 0 - 0 0 0 0 4 x 0f f f 7 2 x 0 - 0 0 0 0 2 x 0 5 s2 3 / 4 6 10 1xxx f f f f 5 x 0 - 0 0 0 0 5 x 0f f f f 2 x 0 - 0 0 0 8 2 x 0 6 s2 3 / 4 6 1 10xxx f f f f 6 x 0 - 0 0 0 0 6 x 0f f f 7 3 x 0 - 0 0 0 0 3 x 0 7 s6 1 / 2 3 1110xx f f f 7 7 x 0 - 0 0 0 0 7 x 0f f f b 3 x 0 - 0 0 0 8 3 x 0 8 s4 / 8 111100 f f f 9 7 x 0 - 0 0 0 8 7 x 0f f f c 3 x 0 - 0 0 0 c 3 x 0 9 s4 / 8 111101 f f f b 7 x 0 - 0 0 0 a 7 x 0f f f d 3 x 0 - 0 0 0 d 3 x 0 0 1 s8 / 6 1 11111x f f f f 7 x 0 - 0 0 0 c 7 x 0f f f f 3 x 0 - 0 0 0 e 3 x 0 notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range in byte mode is a[17:0, -1]. the address range in word mode is a[17:0]. r o t c e s e z i s ) w k / b k ( s s e r d d a r o t c e s 1 e d o m e t y b e g n a r s s e r d d a 3 , 2 e d o m d r o w e g n a r s s e r d d a 3 , 2 ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s8 / 6 1 00000x f f f 3 0 x 0 - 0 0 0 0 0 x 0f f f 1 0 x 0 - 0 0 0 0 0 x 0 1 s4 / 8 000010 f f f 5 0 x 0 - 0 0 0 4 0 x 0f f f 2 0 x 0 - 0 0 0 2 0 x 0 2 s4 / 8 000011 f f f 7 0 x 0 - 0 0 0 6 0 x 0f f f 3 0 x 0 - 0 0 0 3 0 x 0 3 s6 1 / 2 3 0001xx f f f f 0 x 0 - 0 0 0 8 0 x 0f f f 7 0 x 0 - 0 0 0 4 0 x 0 4 s2 3 / 4 6 0 0 1xxx f f f f 1 x 0 - 0 0 0 0 1 x 0f f f f 0 x 0 - 0 0 0 8 0 x 0 5 s2 3 / 4 6 0 10xxx f f f f 2 x 0 - 0 0 0 0 2 x 0f f f 7 1 x 0 - 0 0 0 0 1 x 0 6 s2 3 / 4 6 0 1 1xxx f f f f 3 x 0 - 0 0 0 0 3 x 0f f f f 1 x 0 - 0 0 0 8 1 x 0 7 s2 3 / 4 6 10 0xxx f f f f 4 x 0 - 0 0 0 0 4 x 0f f f 7 2 x 0 - 0 0 0 0 2 x 0 8 s2 3 / 4 6 10 1xxx f f f f 5 x 0 - 0 0 0 0 5 x 0f f f f 2 x 0 - 0 0 0 8 2 x 0 9 s2 3 / 4 6 1 10xxx f f f f 6 x 0 - 0 0 0 0 6 x 0f f f 7 3 x 0 - 0 0 0 0 3 x 0 0 1 s2 3 / 4 6 111xxx f f f f 7 x 0 - 0 0 0 0 7 x 0f f f f 3 x 0 - 0 0 0 8 3 x 0 notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range in byte mode is a[17:0, -1]. the address range in word mode is a[17:0].
7 rev. 1.0/nov. 01 HY29LV400 table 3. HY29LV400 normal bus operations 1 notes: 1. l = v il , h = v ih , x = don ? t care (l or h), d out = data out, d in = data in. see dc characteristics for voltage levels. 2. address is a[17:0, -1] in byte mode and a[17:0] in word mode. 3. dq[15] is the a[-1] input in byte mode (byte# = l). n o i t a r e p o # e c # e o # e w # t e s e r s s e r d d a 2 ] 0 : 7 [ q d ] 8 : 5 1 [ q d 3 h = # e t y b l = # e t y b d a e rllhha n i d t u o d t u o z - h g i h e t i r wlhlha n i d n i d n i z - h g i h e l b a s i d t u p t u olhhhxz - h g i hz - h g i hz - h g i h y b d n a t s l a m r o n # e chxxhxz - h g i hz - h g i hz - h g i h y b d n a t s p e e d # e cv c c v 3 . 0 xxv c c v 3 . 0 x z - h g i hz - h g i hz - h g i h t e s e r e r a w d r a h ) y b d n a t s l a m r o n ( xxx l x z - h g i hz - h g i hz - h g i h t e s e r e r a w d r a h ) y b d n a t s p e e d ( xxxv s s v 3 . 0 x z - h g i hz - h g i hz - h g i h table 4. HY29LV400 bus operations requiring high voltage 1, 2 notes: 1. l = v il , h = v ih , x = don ? t care (l or h). see dc characteristics for voltage levels. 2. address bits not specified are don ? t care. 3. see text and for additional information. 4. sa = sector address. see tables 1 and 2. 5. dq[15] is the a[-1] input in byte mode (byte# = l). 6. normal read, write and output disable operations are used in this mode. see table 3. n o i t a r e p o 3 # e c # e o # e w # t e s e r ] 2 1 : 9 1 [ a ] 9 [ a ] 6 [ a ] 1 [ a ] 0 [ a ] 0 : 7 [ q d ] 8 : 5 1 [ q d # e t y b h = # e t y b l = 5 t c e t o r p r o t c e slhlv d i a s 4 xlhld n i d / t u o xx t c e t o r p n u r o t c e slhlv d i xxhhld n i d / t u o xx r o t c e s y r a r o p m e t t c e t o r p n u 6 - -- -- -v d i - -- -- -- -- -- -- -- - e d o c r e r u t c a f u n a mllhhxv d i lll d a x 0xz - h g i h e c i v e d e d o c b 0 0 4 v l 9 2 y h llh h x v d i llh a b x 0 2 2 x 0z - h g i h t 0 0 4 v l 9 2 y h 9 b x 0 n o i t c e t o r p r o t c e s n o i t a c i f i r e v llh h a s 4 v d i lhl = 0 0 x 0 d e t c e t o r p n u xz - h g i h = 1 0 x 0 d e t c e t o r p
8 rev. 1.0/nov. 01 HY29LV400 write operation certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29LV400. writes to the device are performed by placing the byte or word address on the device ? s address inputs while the data to be written is input on dq[15:0] (byte# = high) or dq[7:0] (byte# = low). the host system must drive the ce# and we# pins low and drive oe# high for a valid write operation to take place. all addresses are latched on the falling edge of we# or ce#, whichever hap- pens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the ? device commands ? section of this data sheet provides details on the specific device commands implemented in the HY29LV400. standby operation when the system is not reading or writing to the device, it can place the HY29LV400 in the standby mode. in this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the oe# input. the standby mode can be invoked using two methods. the device enters the ce# deep standby mode when the ce# and reset# pins are both held at v cc 0.3v. note that this is a more restricted volt- age range than v ih . if both ce# and reset# are held at v ih , but not within v cc 0.3v, the device will be in the ce# normal standby mode, but the standby current will be greater. the device enters the reset# deep standby mode when the reset# pin is held at v ss 0.3v. if reset# is held at v il but not within v ss 0.3v, the device will be in the reset# normal standby mode, but the standby current will be greater. see reset operation for additional information. the device requires standard access time (t ce ) for read access when the device is in either of the standby modes, before it is ready to read data. note : if the device is deselected during an erase or programming operation, it continues to draw active current until the operation is completed. sleep mode the sleep mode automatically minimizes device power consumption. this mode is automatically entered when addresses remain stable for t acc + 30 ns (typical) and is independent of the state of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note: sleep mode is entered only when the device is in read mode. it is not entered if the device is executing an automatic algorithm, if it is in erase suspend mode, or during receipt of a command sequence. output disable operation when the oe# input is at v ih , output data from the device is disabled and the data bus pins are placed in the high impedance state. reset operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. if an operation was interrupted by the as- sertion of reset#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. current is reduced for the duration of the reset# pulse as described in the standby operation sec- tion above. if reset# is asserted during a program or erase operation, the ry/by# pin remains low (busy) until the internal reset operation is complete, which re- quires a time of t ready (during automatic algo- rithms). the system can thus monitor ry/by# to determine when the reset operation completes, and can perform a read or write operation t rb after ry/by# goes high. if reset# is asserted when a program or erase operation is not executing (ry/ by# pin is high), the reset operation is completed within a time of t rp . in this case, the host can per- form a read or write operation t rh after the re- set# pin returns high . the reset# pin may be tied to the system reset signal. thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the flash memory.
9 rev. 1.0/nov. 01 HY29LV400 sector protect operation the hardware sector protection feature disables both program and erase operations in any sector or combination of sectors. this function can be implemented either in-system or by using program- ming equipment. the sector protect procedure requires v id on the reset# pin and uses standard microprocessor bus cycle timing to implement sector protection. the flow chart in figure 1 illustrates the algorithm. the HY29LV400 is shipped with all sectors un- protected. it is possible to determine whether a sector is protected or unprotected. see the elec- tronic id mode section for details. sector unprotect operation the hardware sector unprotection feature re-en- ables both program and erase operations in pre- viously protected sectors. this function can be implemented either in-system or by using program- ming equipment. note that to unprotect any sec- tor, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. also, the unprotect procedure will cause all sectors to become unprotected, thus, sectors that require start reset# = v id wait 1 us write 0x60 to device write 0x60 to address wait 150 us write 0x40 to address read from address data = 0x01? protect another sector? yes trycnt = 25? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector protect complete trycnt = 1 set address: a[17:12] = sector to protect a[6] = 0, a[1] = 1, a[0] = 0 figure 1. sector protect algorithm protection must be protected again after the un- protect procedure is run. the sector unprotect procedure requires v id on the reset# pin and uses standard microproces- sor bus cycle timing to implement sector unpro- tection. the flow chart in figure 2 illustrates the algorithm. temporary sector unprotect operation this feature allows temporary unprotection of pre- viously protected sectors to allow changing the data in-system. sector unprotect mode is activated by setting the reset# pin to v id . while in this mode, formerly protected sectors can be pro- grammed or erased by invoking the appropriate commands (see device commands section). once v id is removed from reset#, all the previ- ously protected sectors are protected again. fig- ure 3 illustrates the algorithm. electronic id operation (high voltage method) the electronic id mode provides manufacturer and device identification and sector protection verifi- cation through codes output on dq[15:0]. this mode is intended primarily for programming equip- ment to automatically match a device to be pro-
10 rev. 1.0/nov. 01 HY29LV400 start (note: all sectors must be protected prior to unprotecting any sector) trycnt = 1 snum = 0 reset# = v id wait 1 us write 0x60 to device write 0x60 to address set address: a[17:12] = sector snum a[6] = 1, a]1] = 1, a]0] = 0 write 0x40 to address read from address data = 0x00? snum = 10? yes trycnt = 1000? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector unprotect complete snum = snum + 1 wait 15 ms set address: a[6] = 1, a]1] = 1, a]0] = 0 figure 2. sector unprotect algorithm start reset# = v id (all protected sectors become unprotected) perform program or erase operations reset# = v ih (all previously protected sectors return to protected state) temporary sector unprotect complete figure 3. temporary sector unprotect algorithm grammed with its corresponding programming al- gorithm. two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], with additional requirements for obtain- ing specific data items listed in table 4. the elec- tronic id data can also be obtained by the host through specific commands issued via the com- mand register, as described in the ? device com- mands ? section of this data sheet. while in the high-voltage electronic id mode, the system may read at specific addresses to obtain certain device identification and status information: a read cycle at address 0xxxx00 retrieves the manufacturer code. a read cycle at address 0xxxx01 in word mode or 0xxxx02 in byte mode returns the device code. a read cycle containing a sector address (sa) in a[17:12] and the address 0x02 in word mode or 0x04 in byte mode, returns 0x01 if that sec- tor is protected, or 0x00 if it is unprotected.
11 rev. 1.0/nov. 01 HY29LV400 device commands device operations are initiated by writing desig- nated address and data command sequences into the device. addresses are latched on the falling edge of we# or ce#, whichever happens later. data is latched on the rising edge of we# or ce#, whichever happens first. a command sequence is composed of one, two or three of the following sub-segments: an unlock cycle , a command cycle and a data cycle . table 5 summarizes the composition of the valid command sequences implemented in the HY29LV400, and these sequences are fully described in table 6 and in the sections that follow. writing incorrect address and data values or writ- ing them in the improper sequence resets the HY29LV400 to the read mode. reading data the device automatically enters the read mode after device power-up, after the reset# input is asserted and upon the completion of certain com- mands. commands are not required to retrieve data in this mode. see read operation section for additional information. reset command writing the reset command resets the sectors to the read or erase-suspend mode. address bits are don ? t cares for this command. as described above, a reset command is not nor- mally required to begin reading array data. how- ever, a reset command must be issued in order to read array data in the following cases: if the device is in the electronic id mode, a reset command must be written to return to the read mode. if the device was in the erase suspend mode when the device entered the electronic id mode, writing the reset command returns the device to the erase suspend mode. note: when in the electronic id bus operation mode, the device returns to the read mode when v id is removed from the a[9] pin. the reset command is not required in this case. if dq[5] (exceeded time limit) goes high dur- ing a program or erase operation, a reset com- mand must be invoked to return the sectors to d n a m m o c e c n e u q e s s e l c y c s u b f o r e b m u n k c o l n u d n a m m o c a t a d t e s e r010 d a e r001 e t o n m a r g o r p d r o w / e t y b211 s s a p y b k c o l n u210 s s a p y b k c o l n u t e s e r 01 1 s s a p y b k c o l n u m a r g o r p d r o w / e t y b 01 1 e s a r e p i h c411 e s a r e r o t c e s41) 2 e t o n ( 1 d n e p s u s e s a r e010 e m u s e r e s a r e010 d i c i n o r t c e l e213 e t o n notes: 1. any number of flash array read cycles are permitted. 2. additional data cycles may follow. see text. 3. any number of electronic id read cycles are permitted. table 5. composition of command sequences the read mode (or to the erase suspend mode if the device was in erase suspend when the program command was issued). the reset command may also be used to abort certain command sequences: in a sector erase or chip erase command se- quence, the reset command may be written at any time before erasing actually begins, in- cluding, for the sector erase command, be- tween the cycles that specify the sectors to be erased (see sector erase command descrip- tion). this aborts the command and resets the device to the read mode. once erasure be- gins, however, the device ignores the reset command until the operation is complete. in a program command sequence, the reset command may be written between the se- quence cycles before programming actually be- gins. this aborts the command and resets the device to the read mode, or to the erase sus- pend mode if the program command sequence is written while the device is in the erase sus- pend mode. once programming begins, how- ever, the device ignores the reset command until the operation is complete.
12 rev. 1.0/nov. 01 HY29LV400 table 6. HY29LV400 command sequences legend: x = don ? t care pa = address of the data to be programmed ra = memory address of data to be read pd = data to be programmed at address pa rd = data read from location ra during the read operation sa = sector address of sector to be erased or verified (see note 3 and tables 1 and 2). notes: see next page for notes. electronic id 6 s e l c y c s u b 3 , 2 , 1 e c n e u q e s d n a m m o c e t i r w s e l c y c t s r i f d n o c e s d r i h t h t r u o f h t f i f h t x i s d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d a e r0a rd r t e s e r 7 1x x x0 f m a r g o r p l a m r o n d r o w 4 5 5 5 a a a a 2 5 5 5 5 5 0 aa pd p e t y ba a a5 5 5a a a s s a p y b k c o l n u d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 0 2 e t y ba a a5 5 5a a a t e s e r s s a p y b k c o l n u2x x x0 9x x x0 0 m a r g o r p s s a p y b k c o l n u 8 d r o w 2x x x0 aa pd p e t y b e s a r e p i h c d r o w 6 5 5 5 a a a a 2 5 5 5 5 5 0 8 5 5 5 a a a a 2 5 5 5 5 5 0 1 e t y ba a a5 5 5a a aa a a5 5 5a a a e s a r e r o t c e s d r o w 6 5 5 5 a a a a 2 5 5 5 5 5 0 8 5 5 5 a a a a 2 5 5a s0 3 e t y ba a a5 5 5a a aa a a5 5 5 d n e p s u s e s a r e 4 1x x x0 b e m u s e r e s a r e 5 1x x x0 3 e d o c r e r u t c a f u n a m d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 0 90 0 xd a e t y ba a a5 5 5a a a e d o c e c i v e d d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 0 9 1 0 x) t o o b m o t t o b ( a b 2 2 , ) t o o b p o t ( 9 b 2 2 e t y ba a a5 5 5a a a2 0 x) t o o b m o t t o b ( a b , ) t o o b p o t ( 9 b y f i r e v t c e t o r p r o t c e s d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 0 9 2 0 x ) a s ( r o t c e s d e t c e t o r p n u = 0 0 r o t c e s d e t c e t o r p = 1 0 e t y ba a a5 5 5a a a4 0 x ) a s (
13 rev. 1.0/nov. 01 HY29LV400 notes for table 6: 1. all values are in hexadecimal. dq[15:8] are don ? t care for unlock and command cycles. 2. all bus cycles are write operations unless otherwise noted. 3. address is a[10:0] in word mode and a[10:0, -1] in byte mode. a[17:11] are don ? t care except as follows: ? for ra and pa, a[17:11] are the upper address bits of the byte to be read or programmed. for the sixth cycle of sector erase, sa = a[17:12] are the sector address of the sector to be erased. for the fourth cycle of sector protect verify, sa = a[17:12] are the sector address of the sector to be verified. 4. the erase suspend command is valid only during a sector erase operation. the system may read and program in non- erasing sectors, or enter the electronic id mode, while in the erase suspend mode. 5. the erase resume command is valid only during the erase suspend mode. 6. the fourth bus cycle is a read cycle. 7. the command is required only to return to the read mode when the device is in the electronic id command mode. it must also be issued to return to read mode if dq[5] goes high during a program or erase operation. it is not required for normal read operations. 8. the unlock bypass command is required prior to the unlock bypass program command. the reset command may be written between the cycles in an electronic id command se- quence to abort that command. as described above, once in the electronic id mode, the reset command must be written to return to the array read mode. program command the system programs the device a word or byte at a time by issuing the appropriate four-cycle pro- gram command sequence as shown in table 6. the sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data. this ini- tiates the automatic program algorithm which au- tomatically provides internally generated program pulses and verifies the programmed cell margin. the host is not required to provide further con- trols or timings during this operation. when the automatic program algorithm is complete, the de- vice returns to the array read mode (or to the erase suspend mode if the device was in erase suspend when the program command was is- sued). several methods are provided to allow the host to determine the status of the programming operation, as described in the write operation status section. commands written to the device during execution of the automatic program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. to ensure data in- tegrity, the aborted program command sequence should be reinitiated once the reset operation is complete. programming is allowed in any sequence. only erase operations can convert a stored ? 0 ? to a ? 1 ? . thus, a bit cannot be programmed from a ? 0 ? back to a ? 1 ? . attempting to do so may halt the opera- tion and set dq[5] to ? 1 ? , or cause the data# poll- ing algorithm to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ? 0 ? . figure 4 illustrates the programming procedure. unlock bypass/bypass program/bypass reset commands unlock bypass provides a faster method for the host system to program the device. as shown in table 6, the unlock bypass command sequence consists of two unlock write cycles followed by a third write cycle containing the unlock bypass command, 0x20. in the unlock bypass mode, a two-cycle unlock bypass program command se- quence is used instead of the standard four-cycle program sequence to invoke a programming op- eration. the first cycle in this sequence contains the unlock bypass program command, 0xa0, and the second cycle specifies the program address and data, thus eliminating the initial two unlock cycles required in the standard program command sequence additional data is programmed in the same manner. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com- mands are valid. to exit the unlock bypass mode, the host must issue the two-cycle unlock bypass reset command sequence shown in table 6. the device then returns to the array read mode. chip erase command the chip erase command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the chip erase command. this sequence invokes the au-
14 rev. 1.0/nov. 01 HY29LV400 tomatic erase algorithm that automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the host system is not required to provide any controls or timings during these operations. commands written to the device during execution of the automatic erase algorithm are ignored. note that a hardware reset immediately terminates the chip erase operation. to ensure data integrity, the aborted chip erase command sequence should be reissued once the reset operation is complete. figure 4. normal and unlock bypass programming procedures figure 5. chip erase procedure start issue chip erase command sequence check erase status (see write operation status section) chip erase complete go to error recovery dq[5] error exit normal exit when the automatic erase algorithm is complete, the device returns to the array read mode. sev- eral methods are provided to allow the host to determine the status of the erase operation, as described in the write operation status section. figure 5 illustrates the chip erase procedure. sector erase command the sector erase command sequence consists of two unlock cycles, followed by the erase com- mand, two additional unlock cycles and then the sector erase data cycle, which specifies the sec- tor to be erased. as described later in this sec- tion, multiple sectors can be specified for erasure with a single command sequence. during sector erase, all specified sectors are erased sequen- tially. the data in sectors not specified for era- sure, as well as the data in any protected sectors, even if specified for erasure, is not affected by the sector erase operation. the sector erase command sequence starts the automatic erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. the device then provides the required number of start enable fast programming? issue unlock bypass command yes no unlock bypass mode? issue unlock bypass program command issue normal program command check programming status (see write operation status section) yes no last word/byte done? yes no setup next address/data for program operation yes no unlock bypass mode? issue unlock bypass reset command programming complete go to error recovery procedure dq[5] error exit programming verified
15 rev. 1.0/nov. 01 HY29LV400 internally generated erase pulses and verifies cell erasure within the proper cell margins. the host system is not required to provide any controls or timings during these operations. after the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sec- tor erase time-out of 50 s (min), measured from the rising edge of the final we# pulse in that bus cycle, begins. during this time-out window, an ad- ditional sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. this buffer may be loaded in any sequence, and the number of sectors specified may be from one sec- tor to all sectors. the only restriction is that the time between these additional data cycles must be less than 50 s, otherwise erasure may begin before the last data cycle is accepted. to ensure that all data cycles are accepted, it is recom- mended that host processor interrupts be disabled during the time that the additional cycles are be- ing issued and then be re-enabled afterwards. if all sectors specified for erasing are protected, the device returns to reading array data after ap- proximately 100 s. if at least one specified sec- tor is not protected, the erase operation erases figure 6. sector erase procedure the unprotected sectors, and ignores the command for the sectors that are protected. the system can monitor dq[3] to determine if the 50 s sector erase time-out has expired, as de- scribed in the write operation status section. if the time between additional sector erase data cycles can be insured to be less than the time- out, the system need not monitor dq[3]. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must then rewrite the command sequence, including any additional sector erase data cycles. once the sec- tor erase operation itself has begun, only the erase suspend command is valid. all other commands are ignored. as for the chip erase command, note that a hard- ware reset immediately terminates the sector erase operation. to ensure data integrity, the aborted sector erase command sequence should be reissued once the reset operation is complete. when the automatic erase algorithm terminates, the device returns to the array read mode. sev- eral methods are provided to allow the host to de- termine the status of the erase operation, as de- scribed in the write operation status section. start yes erase an additional sector? check erase status (see write operation status section) setup first (or next) sector address for erase operation erase complete write first five cycles of sector erase command sequence write last cycle (sa/0x30) of sector erase command sequence sector erase time-out (dq[3]) expired? no yes no go to error recovery dq[5] error exit normal exit sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence
16 rev. 1.0/nov. 01 HY29LV400 figure 6 illustrates the sector erase procedure. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation to read data from, or program data in, any sector not being erased. the command causes the erase opera- tion to be suspended in all sectors specified for erasure. this command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the command se- quence, and is ignored if it is issued during chip erase or programming operations. the HY29LV400 requires a maximum of 20 s to suspend the erase operation if the erase suspend command is issued during sector erasure. how- ever, if the command is written during the time- out, the time-out is terminated and the erase op- eration is suspended immediately. once the erase operation has been suspended, the system can read array data from or program data to any sec- tor not specified for erasure. normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq[7:0]. the host can use dq[7], or dq[6] and dq[2] together, to determine if a sector is actively erasing or is erase- suspended. see the write operation status sec- tion for information on these status bits. after an erase-suspended program operation is complete, the host can initiate another program- ming operation (or read operation) within non-sus- pended sectors. the host can determine the sta- tus of a program operation during the erase-sus- pended state just as in the standard programming operation. the host may also write the electronic id com- mand sequence when the device is in the erase suspend mode. the device allows reading elec- tronic id codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the elec- tronic id mode, the device reverts to the erase suspend mode, and is ready for another valid op- eration. see electronic id mode section for more information. the system must write the erase resume com- mand to exit the erase suspend mode and con- tinue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. electronic id command the electronic id mode provides manufacturer and device identification and sector protection verifi- cation through identifier codes output on dq[7:0]. this mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], as described previously in the device operations section. the electronic id data can also be obtained by the host by invoking the electronic id command, as shown in table 6. this method does not re- quire v id . the electronic id command sequence may be issued while the device is in the read mode or in the erase suspend read mode, that is, except while programming or erasing. the electronic id command sequence is initiated by writing two unlock cycles, followed by the elec- tronic id command. the device then enters the electronic id mode, and the system may read at any address any number of times, without initiat- ing another command sequence. a read cycle at address 0xxxx00 retrieves the manufacturer code. a read cycle at address 0xxxx01 in word mode or 0xxxx02 in byte mode returns the device code. a read cycle containing a sector address (sa) in a[17:12] and the address 0x02 in a[7:0] in word mode (or 0x04 in a[6:0, -1] in byte mode) returns 0x01 if that sector is protected, or 0x00 if it is unprotected. the system must write the reset command to exit the electronic id mode and return to reading ar- ray data.
17 rev. 1.0/nov. 01 HY29LV400 table 7. write and erase operation status summary notes: 1. a valid address is required when reading status information. see text for additional information. 2. dq[5] status switches to a ? 1 ? when a program or erase operation exceeds the maximum timing limit. 3. a ? 1 ? during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. dq[3] is not applicable to the chip erase operation. 4. equivalent to ? no toggle ? because data is obtained in this state. 5. data (dq[7:0]) = 0xff immediately after erasure. 6. programming can be done only in a non-suspended sector (a sector not specified for erasure). e d o m n o i t a r e p o ] 7 [ q d 1 ] 6 [ q d ] 5 [ q d ] 3 [ q d ] 2 [ q d 1 # y b / y r l a m r o n s s e r g o r p n i g n i m m a r g o r p# ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r pa t a da t a d 4 a t a da t a da t a d1 s s e r g o r p n i e s a r e0e l g g o t1 / 0 2 1 3 e l g g o t0 d e t e l p m o c e s a r e 5 a t a da t a d 4 a t a da t a da t a d 4 1 e s a r e d n e p s u s d e d n e p s u s e s a r e n i h t i w d a e r r o t c e s 1e l g g o t o n0a / ne l g g o t1 e s a r e - n o n n i h t i w d a e r r o t c e s d e d n e p s u s a t a da t a da t a da t a da t a d1 s s e r g o r p n i g n i m m a r g o r p 6 # ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r p 6 a t a da t a d 4 a t a da t a da t a d1 write operation status the HY29LV400 provides a number of facilities to determine the status of a program or erase op- eration. these are the ry/by# (ready/busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. table 7 summarizes the status indications and further detail is provided in the subsections which follow. ry/by# - ready/busy# ry/by# is an open-drain output pin that indicates whether a programming or erase automatic algo- rithm is in progress or has completed. a pull-up resistor to v cc is required for proper operation. ry/ by# is valid after the rising edge of the final we# pulse in the corresponding command sequence. if the output is low (busy), the device is actively erasing or programming, including programming while in the erase suspend mode. if the output is high (ready), the device has completed the op- eration and is ready to read array data in the nor- mal or erase suspend modes, or it is in the standby mode. dq[7] - data# polling the data# ( ? data bar ? ) polling bit, dq[7], indicates to the host system whether an automatic algo- rithm is in progress or completed, or whether the device is in erase suspend mode. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. the system must do a read at the program ad- dress to obtain valid programming status informa- tion on this bit. while a programming operation is in progress, the device outputs the complement of the value programmed to dq[7]. when the pro- gramming operation is complete, the device out- puts the value programmed to dq[7]. if a pro- gram operation is attempted within a protected sector, data# polling on dq[7] is active for ap- proximately 1 s, then the device returns to read- ing array data. the host must read at an address within any non- protected sector specified for erasure to obtain valid erase status information on dq[7]. during an erase operation, data# polling produces a ? 0 ? on dq[7]. when the erase operation is complete, or if the device enters the erase suspend mode, data# polling produces a ? 1 ? on dq[7]. if all sec- tors selected for erasing are protected, data# polling on dq[7] is active for approximately 100 s, then the device returns to reading array data. if at least one selected sector is not protected, the erase operation erases the unprotected sectors,
18 rev. 1.0/nov. 01 HY29LV400 and ignores the command for the specified sec- tors that are protected. when the system detects that dq[7] has changed from the complement to true data (or ? 0 ? to ? 1 ? for erase), it should do an additional read cycle to read valid data from dq[7:0]. this is because dq[7] may change asynchronously with respect to the other data bits while output enable (oe#) is as- serted low. figure 7 illustrates the data# polling test algorithm. dq[6] - toggle bit i toggle bit i on dq[6] indicates whether an auto- matic program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the program or erase command sequence, including during the sector start read dq[7:0] at valid address (note 1) dq[7] = data? no yes program/erase complete dq[5] = 1? no yes test for dq[7] = 1? for erase operation read dq[7:0] at valid address (note 1) dq[7] = data? (note 2) no yes test for dq[7] = 1? for erase operation program/erase exceeded time error notes: 1. during programming , the program address. during sector erase , an address within any non-protected sector specified for erasure. during chip erase , an address within any non-protected sector. 2. recheck dq[7] since it may change asynchronously to dq[5]. figure 7. data# polling test algorithm erase time-out. the system may use either oe# or ce# to control the read cycles. successive read cycles at any address during an automatic program algorithm operation (including programming while in erase suspend mode) cause dq[6] to toggle. dq[6] stops toggling when the operation is complete. if a program address falls within a protected sector, dq[6] toggles for approximately one s after the program command sequence is written, then returns to reading array data. while the automatic erase algorithm is operating, successive read cycles at any address cause dq[6] to toggle. dq[6] stops toggling when the erase operation is complete or when the device is placed in the erase suspend mode. the host may use dq[2] to determine which sectors are erasing or erase-suspended (see below). after an erase command sequence is written, if all sectors se- lected for erasing are protected, dq[6] toggles for approximately 100 s, then returns to reading ar- ray data. if at least one selected sector is not pro- tected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sec- tors that are protected. dq[2] - toggle bit ii toggle bit ii, dq[2], when used with dq[6], indi- cates whether a particular sector is actively eras- ing or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. the device toggles dq[2] with each oe# or ce# read cycle. dq[2] toggles when the host reads at addresses within sectors that have been specified for era- sure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. dq[6], by comparison, indicates whether the device is ac- tively erasing or is in erase suspend, but cannot distinguish which sectors are specified for erasure. thus, both status bits are required for sector and mode information. figure 8 illustrates the operation of toggle bits i and ii. dq[5] - exceeded timing limits dq[5] is set to a ? 1 ? when the program or erase time has exceeded a specified internal pulse count
19 rev. 1.0/nov. 01 HY29LV400 limit. this is a failure condition that indicates that the program or erase cycle was not successfully completed. dq[5] status is valid only while dq[7] or dq[6] indicate that the automatic algorithm is in progress. the dq[5] failure condition will also be signaled if the host tries to program a ? 1 ? to a location that is previously programmed to ? 0 ? , since only an erase operation can change a ? 0 ? to a ? 1 ? . for both of these conditions, the host must issue a reset command to return the device to the read mode. dq[3] - sector erase timer after writing a sector erase command sequence, the host may read dq[3] to determine whether or not an erase operation has begun. when the sector erase time-out expires and the sector erase operation commences, dq[3] switches from a ? 0 ? read dq[7:0] at valid address (note 1) dq[6] toggled? no (note 3) yes program/erase complete dq[5] = 1? no yes read dq[7:0] at valid address (note 1) dq[6] toggled? (note 2) no yes program/erase exceeded time error notes : 1. during programming, the program address. during sector erase, an address within any sector scheduled for erasure. 2. recheck dq[6] since toggling may stop at the same time as dq[5] changes from 0 to 1. 3. use this path if testing for program/erase status. 4. use this path to test whether sector is in erase suspend mode. read dq[7:0] at valid address (note 1) start read dq[7:0] dq[2] toggled? no sector being read is in erase suspend read dq[7:0] yes no (note 4) sector being read is not in erase suspend figure 8. toggle bit i and ii test algorithm to a ? 1 ? . refer to the ? sector erase command ? section for additional information. note that the sector erase timer does not apply to the chip erase command. after the initial sector erase command sequence is issued, the system should read the status on dq[7] (data# polling) or dq[6] (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq[3]. if dq[3] is a ? 1 ? , the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than erase suspend) are ignored until the erase operation is complete. if dq[3] is a ? 0 ? , the device will accept a sector erase data cycle to mark an additional sector for erasure. to ensure that the data cycles have been accepted, the system software should check the status of dq[3] prior to and following each subsequent sector erase data cycle. if dq[3] is high on the second status check, the last data cycle might not have been accepted.
20 rev. 1.0/nov. 01 HY29LV400 hardware data protection the HY29LV400 provides several methods of pro- tection to prevent accidental erasure or program- ming which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. these methods are described in the sections that follow. command sequences commands that may alter array data require a sequence of cycles as described in table 6. this provides data protection against inadvertent writes. low v cc write inhibit to protect data during v cc power-up and power- down, the device does not accept write cycles when v cc is less than v lko (typically 2.4 volts). the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by asserting any one of the following conditions: oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power- up. sector protection additional data protection is provided by the HY29LV400 ? s sector protect feature, described previously, which can be used to protect sensitive areas of the flash array from accidental or unau- thorized attempts to alter the data.
21 rev. 1.0/nov. 01 HY29LV400 absolute maximum ratings 4 l o b m y s r e t e m a r a p e u l a v t i n u t g t s e r u t a r e p m e t e g a r o t s 0 5 1 + o t 5 6 -c o t s a i b d e i l p p a r e w o p h t i w e r u t a r e p m e t t n e i b m a 5 2 1 + o t 5 6 -c o v 2 n i v o t t c e p s e r h t i w n i p n o e g a t l o v s s : c c v 1 # t e s e r , # e o , ] 9 [ a 2 s n i p r e h t o l l a 1 0 . 4 + o t 5 . 0 - 5 . 2 1 + o t 5 . 0 - v o t 5 . 0 - c c 5 . 0 + v v v i s o t n e r r u c t i u c r i c t r o h s t u p t u o 3 0 0 2a m notes: 1. minimum dc voltage on input or i/o pins is ? 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 9. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10. 2. minimum dc input voltage on pins a[9], oe#, and reset# is -0.5 v. during voltage transitions, a[9], oe#, and reset# may undershoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on pin a[9] is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output at a time may be shorted to v ss . duration of the short circuit should be less than one second. 4. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions 1 l o b m y s r e t e m a r a p e u l a v t i n u t a : e r u t a r e p m e t g n i t a r e p o t n e i b m a s e c i v e d e r u t a r e p m e t l a i c r e m m o c s e c i v e d e r u t a r e p m e t l a i r t s u d n i 0 7 + o t 0 5 8 + o t 0 4 - c o c o v c c : e g a t l o v y l p p u s g n i t a r e p o n o i s r e v 5 5 - s n o i s r e v r e h t o 6 . 3 + o t 0 . 3 + 6 . 3 + o t 7 . 2 + v v notes: 1. recommended operating conditions define those limits between which the functionality of the device is guaranteed. 2.0 v v cc + 0.5 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 9. maximum undershoot waveform figure 10. maximum overshoot waveform 0.8 v - 0.5 v - 2.0 v 20 ns 20 ns 20 ns
22 rev. 1.0/nov. 01 HY29LV400 dc characteristics r e t e m a r a p n o i t p i r c s e d p u t e s t s e t 2 n i m p y t x a m t i n u i i l t n e r r u c d a o l t u p n iv n i v = s s v o t c c 0 . 1 a i t i l t n e r r u c d a o l t u p n i ] 9 [ av 5 . 2 1 = ] 9 [ a5 3a i o l t n e r r u c e g a k a e l t u p t u ov t u o v = s s v o t c c 0 . 1 a i 1 c c v c c t n e r r u c d a e r e v i t c a 1 v = # e c l i , v = # e o h i , e d o m e t y b z h m 572 1a m z h m 124a m v = # e c l i , v = # e o h i , e d o m d r o w z h m 572 1a m z h m 124a m i 2 c c v c c t n e r r u c e t i r w e v i t c a 4 , 3 v = # e c l i ,v = # e o h i 5 10 3a m i 3 c c v c c p e e d d e l l o r t n o c # e c t n e r r u c y b d n a t s v = # e c c c , v 3 . 0 v = # t e s e r c c v 3 . 0 2 . 05a i 4 c c v c c p e e d d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s v = # t e s e r s s v 3 . 0 2 . 05a i 5 c c e d o m p e e l s c i t a m o t u a t n e r r u c , 5 v h i v = c c , v 3 . 0 v l i v = s s v 3 . 0 2 . 05a i 6 c c v c c l a m r o n d e l l o r t n o c # e c t n e r r u c y b d n a t s 2 v = # t e s e r = # e c h i 1a m i 7 c c v c c d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s l a m r o n 2 v = # t e s e r l i 1a m v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n ix 7 . 0v c c v c c 3 . 0 +v v d i d n a d i c i n o r t c e l e r o f e g a t l o v t c e t o r p n u r o t c e s y r a r o p m e t v c c v 3 . 3 =5 . 1 15 . 2 1v v l o e g a t l o v w o l t u p t u o v c c v = c c , n i m i l o a m 0 . 4 = 5 4 . 0v v 1 h o e g a t l o v h g i h t u p t u o v c c v = c c , n i m i h o a m 0 . 2 - = x 5 8 . 0v c c v v 2 h o v c c v = c c , n i m i h o 0 0 1 - =a v c c 4 . 0 -v v o k l v w o l c c e g a t l o v t u o k c o l 4 3 . 25 . 2v notes: 1. the i cc current is listed is typically less than 2 ma/mhz with oe# at v ih . typical v cc is 3.0 v. 2. all specifications are tested with v cc = v cc max unless otherwise noted. 3. i cc active while the automatic erase or automatic program algorithm is in progress. 4. not 100% tested. 5. automatic sleep mode is enabled when addresses remain stable for t acc + 30 ns (typical).
23 rev. 1.0/nov. 01 HY29LV400 dc characteristics zero power flash figure 11. i cc1 current vs. time (showing active and automatic sleep currents) note: addresses are switching at 1 mhz. figure 12. typical i cc1 current vs. frequency note: t = 25 c. 0 500 1000 1500 2000 2500 3000 3500 4000 0 5 10 15 20 time in ns supply current in ma 12345 0 2 4 6 frequency in mhz supply current in ma 8 2.7 v 3.6 v
24 rev. 1.0/nov. 01 HY29LV400 test conditions table 12. test specifications figure 13. test setup measurement level 1.5 v output i nput 1.5 v 0.0 v 3.0 v figure 14. input waveforms and measurement levels t s e t n o i t i d n o c 5 5 - 0 7 - 0 9 - t i n u d a o l t u p t u oe t a g l t t 1 c ( e c n a t i c a p a c d a o l t u p t u o l )0 30 0 1f p s e m i t l l a f d n a e s i r t u p n i5s n l e v e l w o l l a n g i s t u p n i0 . 0v l e v e l h g i h l a n g i s t u p n i0 . 3v t n e m e r u s a e m g n i m i t w o l l e v e l l a n g i s 5 . 1v t n e m e r u s a e m g n i m i t h g i h l e v e l l a n g i s 5 . 1v 6.2 kohm c l 2.7 kohm + 3.3v device under test all diodes are 1n3064 or equivalent m r o f e v a w s t u p n i s t u p t u o y d a e t s l o t h m o r f g n i g n a h c h o t l m o r f g n i g n a h c d e t t i m r e p e g n a h c y n a , e r a c t ' n o dn w o n k n u e t a t s , g n i g n a h c y l p p a t o n s e o d e t a t s e c n a d e p m i h g i h s i e n i l r e t n e c ) z h g i h ( key to switching waveforms note: timing measurements are made at the reference lev- els specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurement is made
25 rev. 1.0/nov. 01 HY29LV400 ac characteristics read operations notes: 1. not 100% tested. addresses stable t rc t acc output valid t oe t ce t oeh t oh t df ry/by# 0 v reset# outputs we# oe# ce# addresses figure 15. read operation timings r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t v a v a t c r e m i t e l c y c d a e r 1 n i m5 50 70 9s n t v q v a t c c a y a l e d t u p t u o o t s s e r d d a v = # e c l i v = # e o l i x a m5 50 70 9s n t v q l e t e c y a l e d t u p t u o o t e l b a n e p i h cv = # e o l i x a m5 50 70 9s n t z q h e t f d z h g i h t u p t u o o t e l b a n e p i h c 1 x a m5 25 20 3s n t v q l g t e o y a l e d t u p t u o o t e l b a n e t u p t u ov = # e c l i x a m0 30 35 3s n t z q h g t f d z h g i h t u p t u o o t e l b a n e t u p t u o 1 x a m5 25 20 3s n t h e o e l b a n e t u p t u o e m i t d l o h 1 d a e rn i m0s n d n a e l g g o t g n i l l o p # a t a d n i m0 1s n t x q x a t h o # e c , s e s s e r d d a m o r f e m i t d l o h t u p t u o t s r i f s r u c c o r e v e h c i h w , # e o r o 1 n i m0s n
26 rev. 1.0/nov. 01 HY29LV400 ac characteristics hardware reset (reset#) notes: 1. not 100% tested. figure 16. reset# timings reset timings not during automatic algorithms reset timings during automatic algorithms ry/by# 0 v t rp t ready ce#, oe# reset# t rh ry/by# t rp t ready ce#, oe# reset# t rb r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t y d a e r c i t a m o t u a g n i r u d ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a 1 x a m0 2s t y d a e r g n i r u d t o n ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a c i t a m o t u a 1 x a m0 0 5s n t p r h t d i w e s l u p # t e s e rn i m0 0 5s n t h r d a e r e r o f e b e m i t h g i h # t e s e r 1 n i m0 5s n t d p r e d o m y b d n a t s o t w o l # t e s e rx a m0 2s t b r e m i t y r e v o c e r # y b / y rn i m0s n
27 rev. 1.0/nov. 01 HY29LV400 ac characteristics word/byte configuration (byte#) r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t l f l e w o l g n i h c t i w s # e t y b o t # e cx a m5s n t h f l e h g i h g n i h c t i w s # e t y b o t # e cx a m5s n t z q l f z - h g i h t u p t u o o t w o l g n i h c t i w s # e t y bx a m5 25 20 3s n t v q h f e v i t c a t u p t u o o t h g i h g n i h c t i w s # e t y bn i m5 50 70 9s n data output dq[14:0] data output dq[7:0] data output dq[7:0] data output dq[14:0] output dq[15] address input a-1 address input a-1 data output dq[15] t elfl t elfh t fhqv t flqz ce# oe# byte# dq[14:0] dq[15]/a-1 byte# dq[14:0] dq[15]/a-1 byte# switching from word to byte mode byte# switching from byte to word mode figure 17. byte# timings for read operations figure 18. byte# timings for write operations t set (t as ) t hold (t ah ) falling edge of the last we# signal ce# we# byte# note: refer to the program/erase operations table for t as and t ah specifications.
28 rev. 1.0/nov. 01 HY29LV400 ac characteristics program and erase operations notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 3.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 2.7 volts (3.0 volts for - 55 version), 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 6 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most bytes/words program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum byte/word program time specified is exceeded. see write operation status section for additional information. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m5 50 70 9s n t l w v a t s a e m i t p u t e s s s e r d d an i m0s n t x a l w t h a e m i t d l o h s s e r d d an i m5 35 45 4s n t h w v d t s d e m i t p u t e s a t a dn i m5 35 35 4s n t x d h w t h d e m i t d l o h a t a dn i m0s n t l w h g t l w h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0s n t l w l e t s c e m i t p u t e s # e cn i m0s n t h e h w t h c e m i t d l o h # e cn i m0s n t h w l w t p w h t d i w e s l u p e t i r wn i m5 35 35 3s n t l w h w t h p w h g i h h t d i w e s l u p e t i r wn i m0 3s n t 1 h w h w t 1 h w h w n o i t a r e p o g n i m m a r g o r p 3 , 2 , 1 e d o m e t y b p y t9s x a m0 0 3s e d o m d r o w p y t1 1s x a m0 6 3s n o i t a r e p o g n i m m a r g o r p p i h c 5 , 3 , 2 , 1 e d o m e t y b p y t5 . 4c e s x a m5 . 3 1c e s e d o m d r o w p y t9 . 2c e s x a m7 . 8c e s t 2 h w h w t 2 h w h w n o i t a r e p o e s a r e r o t c e s 4 , 2 , 1 p y t5 . 0c e s x a m0 1c e s t 3 h w h w t 3 h w h w n o i t a r e p o e s a r e p i h c 4 , 2 , 1 p y t5 c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e 1 p y t0 0 0 , 0 0 0 , 1s e l c y c n i m0 0 0 , 0 0 1s e l c y c t s c v v c c e m i t p u t e s 1 n i m0 5s t b r # y b / y r m o r f e m i t y r e v o c e rn i m0s n t y s u b y a l e d # y b / y r o t h g i h # e wn i m0 9s n
29 rev. 1.0/nov. 01 HY29LV400 ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. commands shown are for word mode operation. 3. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 19. program operation timings addresses ce# t wc 0x555 pa pa pa oe# t as t ah t wph t wp t ghwl t cs we# data t ds t dh 0xa0 pd status t whwh1 ry/by# t busy t rb t vcs v cc program command sequence (last two cycles) read status data (last two cycles) d out t ch
30 rev. 1.0/nov. 01 HY29LV400 ac characteristics notes: 1. sa =sector address (for sector erase), va = valid address for reading status data (see write operation status section), d out is the true data at the read address.(0xff after an erase operation). 2. commands shown are for word mode operation. 3. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 20. sector/chip erase operation timings addresses ce# t wc 0x2aa va va sa oe# t as t ah t wph t wp t ghwl t cs t ch we# data t ds t dh 0x55 0x30 status d out t whwh2 or t whwh3 ry/by# t busy t rb t vcs v cc erase command sequence (last two cycles) read status data (last two cycles) address = 0x555 for chip erase data = 0x10 for chip erase
31 rev. 1.0/nov. 01 HY29LV400 ac characteristics notes: 1. va = valid address for reading toggle bits (dq[2], dq[6]) status data (see write operation status section). 2. illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle. figure 22. toggle polling timings (during automatic algorithms) t busy t ch t oe t ce t rc complement complement true valid data status data status data data valid data ry/by# dq[6:0] dq[7] we# oe# ce# addresses va va va t acc t oeh t oh t df notes: 1. va = valid address for reading data# polling status data (see write operation status section). 2. illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. figure 21. data# polling timings (during automatic algorithms) t busy t ch t oe t ce t rc valid status valid status valid status ry/by# dq[6], [2] we# oe# ce# addresses va va va t oeh t oh t df va (second read) (first read) (stops toggling) valid data t acc
32 rev. 1.0/nov. 01 HY29LV400 ac characteristics notes: 1. the system may use ce# or oe# to toggle dq[2] and dq[6]. dq[2] toggles only when read at an address within an erase-suspended sector. figure 23. dq[2] and dq[6] operation r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t r d i v v d i t c e t o r p n u r o t c e s y r a r o p m e t r o f e m i t n o i t i s n a r t 1 n i m0 0 5s n t p s r r o f e m i t p u t e s # t e s e r t c e t o r p n u r o t c e s y r a r o p m e t n i m4 s t s e r v d n a t c e t o r p r o t c e s r o f e m i t p u t e s # t e s e r t c e t o r p n u n i m1s t t o r p e m i t t c e t o r p r o t c e sx a m0 5 1s t r p n u e m i t t c e t o r p n u r o t c e sx a m5 1s m sector protect and unprotect, temporary sector unprotect notes: 1. not 100% tested. figure 24. temporary sector unprotect timings erase complete we# dq[6] dq[2] enter automatic erase erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase suspend t vidr ry/by# we# ce# reset# v id 0 or 3v t rsp t vidr 0 or 3v
33 rev. 1.0/nov. 01 HY29LV400 v id v ih reset# don't care valid * valid * valid * sa, a[6], a[1], a[0] 0x60 0x60 0x40 status data ce# we# oe# t vres t prot sector protect/unprotect verify t unpr note: for sector protect, a[6] = 0, a[1] = 1, a[0] = 0. for sector unprotect, a[6] = 1, a[1] = 1, a[0] = 0. figure 25. sector protect and unprotect timings ac characteristics alternate ce# controlled program and erase operations 2 notes: 1. not 100% tested. 2. see program and erase operations table for program and erase characteristics. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 5 - 0 7 - 0 9 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m5 50 70 9s n t l e v a t s a e m i t p u t e s s s e r d d an i m0s n t x a l e t h a e m i t d l o h s s e r d d an i m5 45 45 4s n t h e v d t s d e m i t p u t e s a t a dn i m5 35 35 4s n t x d h e t h d e m i t d l o h a t a dn i m0s n t l e h g t l e h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0s n t l e l w t s w e m i t p u t e s # e wn i m0s n t h w h e t h w e m i t d l o h # e wn i m0s n t h e l e t p c h t d i w e s l u p # e cn i m5 35 35 3s n t l e h e t h p c h g i h h t d i w e s l u p # e cn i m0 3s n t y s u b y a l e d # y b / y r o t # e cn i m0 9s n
34 rev. 1.0/nov. 01 HY29LV400 ac characteristics 0x555 for program 0x2aa for erase pa for program sa for sector erase 0x555 for chip erase t ws t rh t wh ce# oe# addresses t wc va t as t ah we# data ry/by# t ds status d out t busy t whwh1 or t whwh2 or t whwh3 t dh 0xa0 for program 0x55 for erase pd for program 0x30 for sector erase 0x10 for chip erase reset# t cp t cph t ghel notes: 1. pa = program address, pd = program data, va = valid address for reading program or erase status (see write opera- tion status section), d out = array data read at va. 2. illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. 3. word mode addressing shown. 4. reset# shown only to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 26. alternate ce# controlled write operation timings
35 rev. 1.0/nov. 01 HY29LV400 latchup characteristics notes: 1. includes all pins except v cc . test conditions: v cc = 3.0v, one pin at a time. tsop and psop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions: t a = 25 o c, f = 1.0 mhz. n o i t p i r c s e d m u m i n i m m u m i x a m t i n u v o t t c e p s e r h t i w e g a t l o v t u p n i s s o / i t p e c x e s n i p l l a n o ) # t e s e r d n a # e o , ] 9 [ a g n i d u l c n i ( s n i p 0 . 1 -5 . 2 1v v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i l l a n o0 . 1 -v c c 0 . 1 +v v c c t n e r r u c0 0 1 -0 0 1a m l o b m y s r e t e m a r a p p u t e s t s e t p y t x a m t i n u c n i e c n a t i c a p a c t u p n iv n i 0 =65 . 7f p c t u o e c n a t i c a p a c t u p t u ov t u o 0 =5 . 82 1f p c 2 n i e c n a t i c a p a c n i p l o r t n o cv n i 0 =5 . 79 f p data retention r e t e m a r a p s n o i t i d n o c t s e t m u m i n i m t i n u e m i t n o i t n e t e r a t a d n r e t t a p m u m i n i m c o 0 5 10 1s r a e y c o 5 2 10 2s r a e y
36 rev. 1.0/nov. 01 HY29LV400 package drawings physical dimensions tsop48 - 48-pin thin small outline package (measurements in millimeters) 18.30 18.50 pin 1 id 11.90 12.10 0.25mm (0.0098") bsc 1.20 max 1 24 48 25 19.80 20.20 0.50 bsc 0.95 1.05 0.50 0.70 0 5 o o 0.10 0.21 0.08 0.20 0.05 0.15
37 rev. 1.0/nov. 01 HY29LV400 package drawings physical dimensions fbga48 - 48-ball fine-pitch ball grid array, 6 x 8 mm (measurements in millimeters) note: unless otherwise specified, tolerance = 0.05 1.10 max 0.20 min c c 0.08 0.76 typ c 0.10 seating plane 8.00 0.10 6.00 0.10 a b c 0.10 c 0.10 c c a1 corner index area 2.10 0.10 1.80 0.10 pin a1 index mark 4.00 bsc 5.60 bsc a b c d e f g h 6 5 4 3 2 1 0.40 bsc 0.80 typ 0.40 bsc 0.30 0.05 ? ? 0.15 m c a b ? 0.08 m c c c
38 rev. 1.0/nov. 01 HY29LV400 0 0 4 v l 9 2 y h xx-xxx s n o i t c u r t s n i l a i c e p s e g n a r e r u t a r e p m e t = k n a l b = i ) c 0 7 + o t 0 ( l a i c r e m m o c ) c 5 8 + o t 0 4 - ( l a i r t s u d n i n o i t p o d e e p s = 5 5 = 0 7 = 0 9 s n 5 5 s n 0 7 s n 0 9 e p y t e g a k c a p = t = f ) p o s t ( e g a k c a p e n i l t u o l l a m s n i h t n i p - 8 4 m m 9 x 8 , ) a g b f ( y a r r a d i r g l l a b h c t i p - e n i f l l a b - 8 4 n o i t a c o l k c o l b t o o b = t = b n o i t p o k c o l b t o o b p o t n o i t p o k c o l b t o o b m o t t o b r e b m u n e c i v e d = 0 0 4 v l 9 2 y hy l n o - t l o v 3 s o m c ) 6 1 x k 6 5 2 / 8 x k 2 1 5 ( t i b a g e m 4 y r o m e m h s a l f e s a r e r o t c e s ordering information hynix products are available in several speeds, packages and operating temperature ranges. the ordering part number is formed by combining a number of fields, as indicated below. refer to the ? valid combinations ? table, which lists the configurations that are planned to be supported in volume. please contact your local hynix representative or distributor to confirm current availability of specific configura- tions and to determine if additional configurations have been released. valid combinations note: 1. the complete part number is formed by appending the suffix shown in the table above to the device number. for example, the part number for a 90 ns, top boot block, industrial temperature range device in the tsop package is HY29LV400tt-90i . d e e p s d n a e g a k c a p p o s t a g b f e r u t a r e p m e t s n 5 5 s n 0 7 s n 0 9 s n 5 5 s n 0 7 s n 0 9 l a i c r e m m o c5 5 - t0 7 - t0 9 - t5 5 - f0 7 - f0 9 - f l a i r t s u d n ii 5 5 - ti 0 7 - ti 0 9 - ti 5 5 - fi 0 7 - fi 0 9 - f
39 rev. 1.0/nov. 01 HY29LV400
40 rev. 1.0/nov. 01 HY29LV400 important notice ? 2001 by hynix semiconductor america. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of hynix semiconductor inc. or hynix semiconductor america (collec- tively ? hynix ? ). the information in this document is subject to change without notice. hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. devices sold by hynix are covered by warranty and patent in- demnification provisions appearing in hynix terms and condi- tions of sale only. hynix makes no warranty, express, statu- tory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. hynix makes no war- ranty of merchantability or fitness for any purpose. hynix ? s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific writ- ten agreement pertaining to such intended use is executed between the customer and hynix prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. d r o c e r n o i s i v e r . v e r e t a d s l i a t e d 0 . 11 0 / 0 1. e s a e l e r l a i t i n i flash memory business unit, korea flash memory business unit, hq hynix semiconductor inc. hynix semiconductor inc. 891, daechi-dong 3101 north first street kangnam-gu san jose, ca 95134 seoul, korea usa telephone: +82-2-3459-5980 telephone: (408) 232-8800 fax: +82-2-3459-5988 fax: (408) 232-8805 http://www.hynix.com http://www.us.hynix.com

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